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| a Nonvolatile Memory, 1024-Position Digital Potentiometers AD5231* FUNCTIONAL BLOCK DIAGRAM CS CLK SDI GND SDI SERIAL INTERFACE EEMEM1 ADDR DECODE RDAC REGISTER FEATURES Nonvolatile Memory1 Preset Maintains Wiper Settings 1024-Position Resolution Full Monotonic Operation 10 k , 50 k , and 100 k Terminal Resistance Permanent Memory Write-Protection Wiper Settings Read Back Linear Increment/Decrement Log Taper Increment/Decrement Push Button Increment/Decrement Compatible SPI Compatible Serial Interface with Readback Function 3 V to 5 V Single Supply or 2.5 V Dual Supply 28 Bytes User Nonvolatile Memory for Constant Storage 100 Year Typical Data Retention TA = 55 C APPLICATIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage to Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Power Supply Adjustment Low Resolution DAC Replacement AD5231 RDAC VDD A W B SDO WP RDY SDO EEMEM CONTROL DIGITAL REGISTER 2 O1 DIGITAL OUTPUT BUFFER O2 EEMEM2 28 BYTES USER EEMEM PR VSS 100 RWA(D), RWB(D) - Percent of Nominal - % RAB RWA RWB 75 GENERAL DESCRIPTION 50 The AD5231 provides nonvolatile memory digitally controlled potentiometers2 with 1024-position resolution. These devices perform the same electronic adjustment function as a mechanical potentiometer. The AD5231's versatile programming via a standard 3-wire serial interface allows 16 modes of operation and adjustment, including scratch pad programming, memory storing and retrieving, increment/decrement, log taper adjustment, wiper setting read back, and extra user-defined EEMEM. In the scratch pad programming mode, a specific setting can be programmed directly to the RDAC2 register, which sets the resistance at terminals W-A and W-B. The RDAC register can also be loaded with a value previously stored in the EEMEM1 register. The value in the EEMEM can be changed or protected. When changes are made to the RDAC register, the value of the new setting can be saved into the EEMEM. Thereafter, such value will be transferred automatically to the RDAC register during system power ON. It is enabled by the internal preset strobe. EEMEM can also be retrieved through direct programming and external preset pin control. 25 0 0 256 512 CODE - Decimal 768 1023 Figure 1. RWA(D) and RWB(D) vs. Decimal Code Other operations include linear step increment and decrement commands such that the setting in the RDAC register can be moved UP or DOWN, one step at a time. For logarithmic changes in wiper setting, a left/right bit shift command adjusts the level in 6 dB steps. The AD5231 is available in thin TSSOP-16 package. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +85C. NOTES 1 The terms Nonvolatile Memory and EEMEM are used interchangeably. 2 The terms Digital Potentiometer and RDAC are used interchangeably. *Patent pending REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001 AD5231-SPECIFICATIONS ELECTRICAL CHARACTERISTICS 10 k , 50 k , 100 k (VDD = 3 V Parameter DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity 2 Resistor Integral Nonlinearity 2 Nominal Resistor Tolerance Resistance Temperature Coefficient Wiper Resistance VERSIONS Min Typ1 Max Unit 10% or 5 V 10% and VSS = 0 V, VA = +VDD, VB = 0 V, -40 C < TA < +85 C, unless otherwise noted.) Symbol Conditions R-DNL R-INL RWB RAB/ T RW RWB, VA = NC, Monotonic RWB, VA = NC D = 3FFH IW = 100 A, VDD = 5.5 V, Code = Half-Scale IW = 100 A, VDD = 3 V, Code = Half-Scale -1 -0.2 -40 1/2 600 15 50 +1.8 +0.2 +20 100 LSB % FS % ppm/C DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Resolution Differential Nonlinearity3 Integral Nonlinearity3 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Terminal Voltage Range4 Capacitance5 A, B Capacitance5 W Common-Mode Leakage Current 5, 6 DIGITAL INPUTS and OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Logic High Input Logic Low Output Logic High (SDO, RDY) Output Logic Low Input Current Input Capacitance5 Output Current5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Programming Mode Current Read Mode Current7 Negative Supply Current Power Dissipation8 Power Supply Sensitivity 5 IO IOL DYNAMIC CHARACTERISTICS 5, 9 Bandwidth Total Harmonic Distortion Total Harmonic Distortion N DNL INL VW/ T VWFSE VWZSE VA, B, W CA, B CW ICM VIH VIL VIH VIL VIH VIL VOH VOL IIL CIL IO1, IO2 Monotonic, TA = 25C Monotonic, TA = -40C or +85C Code = Half-Scale Code = Full-Scale Code = Zero-Scale 10 -1 -1 -0.4 -3 0 VSS 1/2 15 +1 +1.25 +0.4 0 +1.5 VDD Bits LSB LSB % FS ppm/C % FS % FS V pF pF f = 1 MHz, Measured to GND, Code = Half-Scale f = 1 MHz, Measured to GND, Code = Half-Scale VW = VDD/2 With Respect to GND, V DD = 5 V With Respect to GND, V DD = 5 V With Respect to GND, V DD = 3 V With Respect to GND, V DD = 3 V With Respect to GND, VDD = +2.5 V, VSS = -2.5 V With Respect to GND, VDD = +2.5 V, VSS = -2.5 V RPULL-UP = 2.2 k to 5 V IOL = 1.6 mA, VLOGIC = 5 V VIN = 0 V or VDD VDD = 5 V, VSS = 0 V, TA = 25C VDD = 2.5 V, VSS = 0 V, TA = 25C VSS = 0 V VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = +2.5 V, VSS = -2.5 V VIH = VDD or VIL = GND VDD = 5 V 10% -3 dB, R = 10 k/50 k/100 k VA = 1 VRMS, VB = 0 V, f = 1 kHz, RAB = 10 k VA = 1 VRMS, VB = 0 V, f = 1 kHz, RAB = 50 k, 100 k 2.7 2.25 0.3 2.4 50 50 0.01 1 A V V V V V 0.8 2.1 0.6 2.0 0.5 4.9 0.4 2.5 4 50 7 5.5 2.75 10 9 10 0.05 0.01 V V V A pF mA mA V V A mA mA A mW %/% kHz % % VDD VDD/VSS IDD IDD(PG) IDD(XFR) ISS PDISS PSS BW THDW THDW 2.7 40 3 0.5 0.018 0.002 370/85/44 0.022 0.045 -2- REV. 0 AD5231 Parameter VW Settling Time Symbol tS Conditions VA = VDD, VB = 0 V, VW = 0.50% Error Band, Code 000H to 200H For RAB = 10 k/50 k/100 k Min Typ1 1.2/3.7/7 Max Unit s Resistor Noise Voltage eN_WB RWB = 5 k, f = 1 kHz 9 nV/Hz NOTES 1 Typicals represent average readings at 25 C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. I W ~ 50 A @ VDD = +2.7 V and IW ~ 400 A @ VDD = +5 V for the RAB = 10 k version, IW ~ 50 A for the RAB = 50 k and I W ~ 25 A for the RAB = 100 k version. See test circuit Figure 12. 3 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = V SS. DNL specification limits of -1 LSB minimum are Guaranteed Monotonic operating conditions. See test circuit Figure 13. 4 Resistor terminals A, B, and W have no limitations on polarity with respect to each other. Dual Supply Operat ion enables ground-referenced bipolar signal adjustment. 5 Guaranteed by design and not subject to production test. 6 Common-mode leakage current is a measure of the dc leakage from any terminal B and W to a common-mode bias level of V DD/2. 7 Transfer (XFR) Mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 19. 8 PDISS is calculated from (I DD VDD) + (ISS VSS). 9 All dynamic characteristics use V DD = +2.5 V and V SS = -2.5 V. Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS 10 k , 50 k , 100 k (VDD = 3 V to 5.5 V and -40 C < TA < +85 C, unless otherwise noted.) Parameter INTERFACE TIMING CHARACTERISTICS2, 3 Clock Cycle Time (tCYC) CS Setup Time CLK Shutdown Time to CS Rise Input Clock Pulsewidth Data Setup Time Data Hold Time CS to SDO-SPI Line Acquire CS to SDO-SPI Line Release CLK to SDO Propagation Delay 4 CLK to SDO Data Hold Time CS High Pulsewidth5 CS High to CS High5 RDY Rise to CS Fall CS Rise to RDY Fall Time Read/Store to Nonvolatile EEMEM 6 CS Rise to Clock Rise/Fall Setup Preset Pulsewidth (Asynchronous) Preset Response Time to RDY High FLASH/EE MEMORY RELIABILITY Endurance7 Data Retention8 VERSIONS Min Typ1 Max Unit Symbol Conditions t1 t2 t3 t 4, t 5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 tPRW tPRESP Clock Level High or Low From Positive CLK Transition From Positive CLK Transition RP = 2.2 k, CL < 20 pF RP = 2.2 k, CL < 20 pF 20 10 1 10 5 5 40 50 50 0 10 4 0 0.1 0.15 25 10 50 70 100 100 Applies to Command 2H, 3H, 9H Not Shown in Timing Diagram PR Pulsed Low to Refreshed Wiper Positions ns ns tCYC ns ns ns ns ns ns ns ns tCYC ns ms ms ms ms s K Cycles Years NOTES 1 Typicals represent average readings at 25 C and VDD = 5 V. 2 Guaranteed by design and not subject to production test. 3 See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V DD = 3 V and 5 V. 4 Propagation delay depends on value of V DD, RPULL_UP, and CL. See applications text. 5 Valid for commands that do not activate the RDY pin. 6 RDY pin low only for commands 2, 3, 8, 9, 10, and the PR hardware pulse: CMD_8 ~ 1 s; CMD_9,10 ~0.12 s; CMD_2,3 ~20 s. Device operation at T A = -40 C and VDD < +3 V extends the save time to 35 s. 7 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at -40 C, +25 C, and +85 C; typical endurance at 25 C is 700,000 cycles. 8 Retention lifetime equivalent at junction temperature (T J) = 55 C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV will derate with junction temperature as shown in Figure 20 in the Flash/EE Memory Description section of this data sheet. The AD5231 contains 9,646 transistors. Die size: 69 mil 115 mil, 7,993 sq. mil. Specifications subject to change without notice. REV. 0 -3- AD5231 CPHA = 1 CS t12 t3 t2 CLK CPOL = 1 t13 t1 t5 t4 t10 t17 t11 LSB OUT t8 SDO t9 * MSB t7 t6 SDI MSB LSB t14 RDY t15 t16 *NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED. THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK. Figure 2a. CPHA = 1 Timing Diagram CS CPHA = 0 t12 t1 t2 CLK CPOL = 0 t3 t5 t17 t13 t4 t8 t10 t11 t9 SDO MSB OUT LSB * t7 t6 SDI MSB IN LSB t14 RDY t15 t16 *NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED. THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK. Figure 2b. CPHA = 0 Timing Diagram -4- REV. 0 AD5231 ABSOLUTE MAXIMUM RATINGS 1 (TA = 25C, unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, -7 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VA, VB, VW to GND . . . . . . . . . . . . . VSS - 0.3 V, VDD + 0.3 V A-B, A-W, B-W Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA Digital Inputs and Output Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD + 0.3 V Operating Temperature Range3 . . . . . . . . . . . -40C to +85C Maximum Junction Temperature (TJ Max) . . . . . . . . . 150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C Thermal Resistance Junction-to-Ambient JA, TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C/W Thermal Resistance Junction-to-Case JC, TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28C/W Package Power Dissipation = (TJ Max - TA)/ JA NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 3 Includes programming of nonvolatile memory ORDERING GUIDE Model AD5231BRU10 AD5231BRU10-REEL7 AD5231BRU50 AD5231BRU50-REEL7 AD5231BRU100 AD5231BRU100-REEL7 RAB Temperature Package Package (k ) Range ( C) Description Option 10 10 50 50 100 100 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 Ordering Quantity 96 1,000 96 1,000 96 1,000 Top Mark* 5231B10 5231B10 5231B50 5231B50 5231BC 5231BC *Line 1 contains ADI logo symbol and the date code YYWW; line 2 contains detail model number listed in this column. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5231 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 -5- AD5231 PIN CONFIGURATION O1 1 CLK 2 SDI 3 SDO 4 16 O2 15 RDY 14 CS 13 PR TOP VIEW GND 5 (Not to Scale) 12 WP AD5231 VSS 6 T7 B8 11 VDD 10 A 9 W PIN FUNCTION DESCRIPTIONS Pin No. 1 2 3 4 Mnemonic O1 CLK SDI SDO Description Nonvolatile Digital Output #1. ADDR(O1) = 1H, data bit position D0 Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first. Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 and 10 activate the SDO output. (See Instruction operation Truth Table, Table III.) Other commands shift out the previously loaded SDI bit pattern delayed by 24 clock pulses. This allows daisy-chain operation of multiple packages. Ground Pin, Logic Ground Reference Negative Supply. Connect to zero volts for single supply applications. Used as digital input during factory test mode. Connect to VDD or VSS. B Terminal of RDAC Wiper Terminal of RDAC. ADDR(RDAC1) = 0H. A Terminal of RDAC1 Positive Power Supply Pin Write Protect Pin. When active low, WP prevents any changes to the present contents except PR and cmd 1 and 8 will refresh the RDAC register from EEMEM. Execute on NOP instruction before returning to WP high. Hardware Override Preset Pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory default loads midscale 51210 until EEMEM loaded with a new value by the user (PR is activated at the logic high transition). Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high. Ready. Active-high open drain output. Identifies completion of commands 2, 3, 8, 9, 10, and PR. Nonvolatile Digital Output #2. ADDR(O2) = 1H, data bit position D1. 5 6 7 8 9 10 11 12 GND VSS T B W A VDD WP 13 PR 14 15 16 CS RDY O2 -6- REV. 0 Typical Performance Characteristics-- AD5231 1.5 TA = +85 C 1.0 1.0 TA = -40 C 2.0 VDD = 5V, VSS = 0V 1.5 INL ERROR - LSB 0.5 TA = +25 C 0 TA = -40 C R-DNL - LSB 0.5 0 -0.5 -1.0 TA = +85 C T A = +25 C -0.5 -1.5 -1.0 0 128 256 384 512 640 768 896 1024 CODE - Decimal -2.0 0 128 256 384 512 640 CODE - Decimal 768 896 1024 TPC 1. INL vs. Code, TA = -40C, +25C, +85C Overlay, RAB = 10 k TPC 4. R-DNL vs. Code, TA = -40C, +25C, +85C Overlay, RAB = 10 k 2.0 VDD = 5V, V SS = 0V RHEOSTAT MODE TEMPCO - ppm/ C 1.5 1.0 DNL ERROR - LSB TA = -40 C 0.5 0 -0.5 -1.0 -1.5 -2.0 0 128 256 384 512 640 768 896 1024 CODE - Decimal TA = +85 C TA = +25 C 3000 VDD = 5.5V, V SS = 0V TA = -40 C TO +85 C 2500 2000 1500 1000 500 0 0 128 256 384 512 640 768 896 1024 CODE - Decimal TPC 2. DNL vs. Code, TA = -40C, +25C, +85C Overlay, RAB = 10 k TPC 5. RWB/ T vs. Code, RAB = 10 k 1.0 POTENTIOMETER MODE TEMPCO - ppm/ C 100 VDD = 5V, VSS = 0V VDD = 5.5V, V SS = 0V 80 TA = -40 C TO +85 C VB = 0V 60 VA = 2.00V 0.5 TA = +85 C 0 TA = +25 C R-INL - LSB 40 20 -0.5 TA = -40 C -1.0 0 128 256 384 512 640 768 896 1024 CODE - Decimal 0 -20 0 128 256 384 512 640 768 896 1024 CODE - Decimal TPC 3. R-INL vs. Code, TA = -40C, +25C, +85C Overlay, RAB = 10 k TPC 6. RWB/ T vs. Code, RAB = 10 k REV. 0 -7- AD5231 60 VDD = 2.7V, V SS = 0V TA = 25 C 50 -2 2 f-3dB = 370kHz, R AB = 10k 0 40 -4 GAIN - dB f-3dB = 44kHz, R = 100k -6 -8 -10 -12 RW - 30 f-3dB = 85kHz, RAB = 50k 20 10 -14 VA = 1mV rms VDD / V SS = 2.5V D = MIDSCALE 100k 10k FREQUENCY - Hz 1M 0 0 128 256 384 512 640 768 896 1024 CODE - Decimal -16 1k TPC 7. Wiper-On Resistance vs. Code TPC 10. -3 Bandwidth vs. Resistance. Test Circuit in Figure 16. 4 0.12 VDD/V SS = 2.5V VA = 1V rms 3 0.10 IDD @ V DD/V SS = 5V/0V THD + NOISE - % CURRENT - A 0.08 2 0.06 RAB = 10k 1 ISS @ V DD/V SS = 5V/0V 0 IDD @ V DD/V SS = 2.7V/0V ISS @ V DD/V SS = 2.7V/0V -1 -40 -20 0 20 40 60 80 100 0.04 0.02 50k 100k 0.00 0.01 0.1 1 FREQUENCY - kHz 10 100 TEMPERATURE - C TPC 8. IDD vs. Temperature, RAB = 10 k TPC 11. Total Harmonic Distortion vs. Frequency 0.25 VDD = 5V VSS = 0V 0.20 0 -5 -10 -15 GAIN - dB CODE = 200H 100H 80H 40H 20H -30 -35 -40 10H 08H IDD - mA 0.15 FULL-SCALE 0.10 ZERO-SCALE 0.05 MIDSCALE 0.00 0 2 4 6 8 10 12 CLOCK FREQUENCY - MHz -20 -25 -45 04H 02H 01H -50 1k 10k 100k FREQUENCY- Hz 1M 10M TPC 9. IDD vs. Clock Frequency, RAB = 10 k TPC 12. Gain vs. Frequency vs. Code, RAB = 10 k. Test Circuit in Figure 18 -8- REV. 0 AD5231 0 CODE = 200H -10 100H 80H -20 40H 20H 10H -40 08H 04H -50 02H 01H -60 1k 10k 100k 1M FREQUENCY - Hz 10 0% 100 90 VDD GAIN - dB -30 VW EXPECTED VALUE MIDSCALE 100 s/DIV 0.5V/DIV TPC 13. Gain vs. Frequency vs. Code, RAB = 50 k. Test Circuit in Figure 18 TPC 16. Power-On Reset, VDD = 2.25 V, Code = 1010101010B 0 CODE = 200H -10 100H 80H -20 40H 20H 10H -40 08H 04H -50 02H 01H -60 1k VOUT - V 2.55 VDD/V SS = 5V/0V CODE = 200H TO 1FFH 2.53 GAIN - dB 2.51 RAB = 10k RAB = 50k RAB = 100k -30 2.49 2.47 2.45 10k 100k 1M 0 5 10 15 TIME - s 20 25 FREQUENCY - Hz TPC 14. Gain vs. Frequency vs. Code, RAB = 100 k. Test Circuit in Figure 18 TPC 17. Midscale Glitch Energy, Code 200H to 1FFH 80 RAB = 100k 70 RAB = 50k 60 50 40 30 20 10 VDD = +5.0V 100mV AC VSS = 0V, VA = 5V, VB = 0V MEASURED AT VW WITH CODE = 200 H 1k 10k 100k FREQUENCY - Hz 1M 10M IDD 20mA/DIV 4ms/DIV 5V/DIV CS RAB = 10k CLK PSRR - dB 5V/DIV SDI 5V/DIV 0 100 TPC 15. PSRR vs. Frequency TPC 18. IDD vs. Time (Save) Program Mode REV. 0 -9- AD5231 100 CS 5V/DIV VA = VB = OPEN TA = 25 C THEORETICAL - IWB_MAX - mA 10 CLK 5V/DIV SDI 5V/DIV IDD* 2mA/DIV 4ms/DIV * SUPPLY CURRENT RETURNS TO MINIMUM POWER CONSUMPTION IF INSTRUCTION #0 (NOP) IS EXECUTED IMMEDIATELY AFTER INSTRUCTION #1 (READ EEMEM) RAB = 10k 1 RAB = 50k 0.1 RAB = 100k 0.01 0 128 256 384 512 640 768 896 1024 CODE - Decimal TPC 19. IDD vs. Time (Read) Program Mode TPC 20. IWB_MAX vs. Code OPERATIONAL OVERVIEW Scratch Pad and EEMEM Programming The AD5231 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of VSS < VTERM < VDD. The basic voltage range is limited to a |VDD - VSS| < 5.5 V. The digital potentiometer wiper position is determined by the RDAC register contents. The RDAC register acts as a scratch pad register allowing as many value changes as necessary to place the potentiometer wiper in the correct position. The scratch pad register can be programmed with any position value using the standard SPI serial interface mode by loading the complete representative data word. Once a desirable position is found this value can be saved into an EEMEM register. Thereafter the wiper position will always be set at that position for any future ONOFF-ON power supply sequence. The EEMEM save process takes approximately 25 ms, during this time the shift register is locked preventing any changes from taking place. The RDY pin indicates the completion of this EEMEM save. There are 16 instructions that facilitate users' programming needs. Refer to Table III. The instructions are: 1. Do Nothing 2. Restore EEMEM Setting to RDAC 3. Save RDAC Setting to EEMEM 4. Save RDAC Setting or User Data to EEMEM 5. Decrement 6 dB 6. Decrement 6 dB 7. Decrement One Step 8. Decrement One Step 9. Reset EEMEM setting to RDAC 10. Read EEMEM to SDO 11. Read Wiper Setting to SDO 12. Write Data to RDAC 13. Increment 6 dB 14. Increment 6 dB 15. Increment One Step 16. Increment One Step The scratch pad register (RDAC register) directly controls the position of the digital potentiometer wiper. When the scratch pad register is loaded with all zeros, the wiper will be connected to the B-Terminal of the variable resistor. When the scratch pad register is loaded with midscale code (1/2 of full-scale position), the wiper will be connected to the middle of the variable resistor. And when the scratch pad is loaded with full-scale code, all ones, the wiper will connect to the A-Terminal. Since the scratch pad register is a standard logic register, there is no restriction on the number of changes allowed. The EEMEM registers have a program erase/write cycle limitation described in the Flash/EEMEM Reliability section. Basic Operation The basic mode of setting the variable resistor wiper position (programming the scratch pad register) is accomplished by loading the serial data input register with the command instruction #11, which includes the desired wiper position data. When the desired wiper position is found, the user would load the serial data input register with the command instruction #2, which makes a copy of the desired wiper position data into the nonvolatile EEMEM register. After 25 ms the wiper position will be permanently stored in the nonvolatile EEMEM location. Table I provides an application-programming example listing the sequence of serial data input (SDI) words and the serial data output appearing at the SDO Pin in hexadecimal format. Table I. Set and Save RDAC Data to EEMEM Register SDI B00100H SDO XXXXXXH Action Loads data 100H into RDAC register, Wiper W moves to 1/4 full-scale position. Saves copy of RDAC register contents into EEMEM register. 20XXXXH B00100H At system power ON, the scratch pad register is automatically refreshed with the value last saved in the EEMEM register. The factory preset EEMEM value is midscale but thereafter, the EEMEM value can be changed by user. -10- REV. 0 AD5231 During operation, the scratch pad (wiper) register can also be refreshed with the current content of the nonvolatile EEMEM register under hardware control by pulsing the PR Pin without activating instruction 1 or 8. Beware that the PR pulse first sets the wiper at midscale when brought to logic zero, and then on the positive transition to logic high, it reloads the RDAC wiper register with the contents of EEMEM. Many additional advanced programming commands are available to simplify the variable resistor adjustment process, See Table III. For example, the wiper position can be changed one step at a time by using the Increment/Decrement instruction or by 6 dB at a time with the Shift Left/Right instruction command. Once an Increment, Decrement, or Shift command has been loaded into the shift register, subsequent CS strobes will repeat this command. This is useful for push button control applications. See the advanced control modes section following the Instruction Operation Truth Table. A serial data output SDO Pin is available for daisy-chaining and for readout of the internal register contents. The serial input data register uses a 24-bit [instruction/address/data] WORD format. EEMEM Protection VDD LOGIC PINS INPUT 300 GND Figure 4a. Equivalent ESD Digital Input Protection VDD INPUT 300 WP Write protect (WP) disables any changes of the scratch pad register contents regardless of the software commands, except that the EEMEM setting can be refreshed and overwritten WP by using commands 1, 8, and PR pulse. Therefore, the writeprotect (WP) Pin provides a hardware EEMEM protection feature. To disable WP, it is recommended to execute a NOP command before returning WP to logic high. Digital Input/Output Configuration GND Figure 4b. Equivalent WP Input Protection Serial Data Interface All digital inputs are ESD-protected high-input impedance that can be driven directly from most digital sources. Active at logic low, PR and WP must be biased to VDD if they are not used. No internal pull-up resistors are present on any digital input pins. The SDO and RDY Pins are open-drain digital outputs where pull-up resistors are needed only if using these functions. A resistor value in the range of 1 k to 10 k is a proper choice which balances the power and switching speed trade off. The equivalent serial data input and output logic is shown in Figure 3. The open drain output SDO is disabled whenever chip select CS is logic high. ESD protection of the digital inputs is shown in Figures 4a and 4b. PR VALID COMMAND COUNTER WP The AD5231 contains a four-wire SPI compatible digital interface (SDI, SDO, CS, and CLK). The AD5231 uses a 24-bit serial data word loaded MSB first. The format of the SPI compatible word is shown in Table II. The chip select CS Pin needs to be held low until the complete data word is loaded into the SDI Pin. When CS returns high the serial data word is decoded according to the instructions in Table III. The Command Bits (Cx) control the operation of the digital potentiometer. The Address Bits (Ax) determine which register is activated. The Data Bits (Dx) are the values that are loaded into the decoded register. Table V provides an address map of the EEMEM locations. The last instruction executed prior to a period of no programming activity should be the No Operation (NOP) instruction. This will place the internal logic circuitry in a minimum power dissipation state. The SPI interface can be used in two slave modes CPHA = 1, CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to the control bits, that dictate SPI timing in these MicroConverters(R) and microprocessors: ADuC812/ADuC824, M68HC11, and MC68HC16R1/916R1. Daisy-Chain Operation COMMAND PROCESSOR AND ADDRESS DECODE 5V RPULLUP CLK SERIAL REGISTER SDO CS SDI GND AD5231 Figure 3. Equivalent Digital Input-Output Logic The Serial Data Output Pin (SDO) serves two purposes. It can be used to readout the contents of the wiper setting and EEMEM values using instructions 10 and 9, respectively. The remaining instructions (#0-#8, #11-#15) are valid for daisy-chaining multiple devices in simultaneous operations. Daisy-chaining minimizes the number of port pins required from the controlling IC (see Figure 5). The SDO Pin contains an open drain N-Ch FET that requires a pull-up resistor, if this function is used. As shown in Figure 5, users need to tie the SDO Pin of one package to the MicroConverter is a registered trademark of Analog Devices Inc. REV. 0 -11- AD5231 SDI Pin of the next package. Users may need to increase the clock period because the pull-up resistor and the capacitive loading at the SDO-SDI interface may require additional time delay between subsequent packages. When two AD5231s are daisy-chained, 48 bits of data are required. The first 24 bits go to U2 and the second 24 bits go to U1. The 24 bits are formatted to contain the 4-bit instruction, followed by the 4-bit address, 6-bit don't care, then the 10 bits of data. (The don't care can be used to store user information. See section Using Additional Internal Nonvolatile EEMEM). The CS should be kept low until all 48 bits are clocked into their respective serial registers. The CS is then pulled high to complete the operation. +V Power-Up Sequence Since there are diodes to limit the voltage compliance at terminals A, B, and W (see Figure 6), it is important to power VDD/VSS first before applying any voltage to terminals A, B, and W. Otherwise, the diode will be forward-biased such that VDD/VSS will be powered unintentionally and may affect the rest of the user's circuit. The ideal power-up sequence is in the following order: GND, VDD, VSS, Digital Inputs, and V A/B/W. The order of powering VA, VB, VW, and digital inputs are not important as long as they are powered after VDD/VSS. Regardless of the power-up sequence and the ramp rates of the power supplies, once VDD/VSS are powered, the power-on reset remains effective, which retrieves EEMEM saved value to RDAC register. Latched Digital Outputs AD5231 C SDI U1 SDO RP 2k SDI AD5231 U2 SDO CS CLK CS CLK A pair of digital outputs, O1 and O2, is available on the AD5231 that provide a nonvolatile logic 0 or logic 1 setting. O1 and O2 are standard CMOS logic outputs (shown in Figure 7). These outputs are ideal to replace functions often provided by DIP switches. In addition, they can be used to drive other standard CMOS logic controlled parts that need an occasional setting change. VDD Figure 5. Daisy Chain Configuration using SDO Terminal Voltage Operation Range The AD5231 positive VDD and negative VSS power supply defines the boundary conditions for proper 3 terminal digital potentiometer operation. Supply signals present on terminals A, B, and W that exceed VDD or VSS will be clamped by the internal forward biased diodes (see Figure 6). The ground pin of the AD5231 device is primarily used as a digital ground reference, which needs to be tied to the PCB's common ground. The digital input control signals to the AD5231 must be referenced to the device ground pin (GND), and satisfy the logic level defined in the specification table of this data sheet. An internal level-shift circuit ensures that the commonmode voltage range of the three terminals extends from VSS to VDD, regardless of the digital input level. VDD OUTPUTS O1 AND O2 PINS GND Figure 7. Logic Outputs O1 and O2 A W B VSS Figure 6. Maximum Terminal Voltages Set by VDD and VSS -12- REV. 0 AD5231 Table II. AD5231 24-Bit Serial Data Word MSB Instruction Byte 0 Data Byte 1 Data Byte 0 LSB RDAC C3 C2 C1 C0 0 0 0 A0 X X X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 EEMEM C3 C2 C1 C0 A3 A2 A1 A0 D D D D D D D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 15 14 13 12 11 10 Command bits are C0 to C3. Address bits are A3 to A0. Data bits D0 to D9 are applicable to RDAC; D0 to D15 are applicable to EEMEM. Command instruction codes are defined in Table III. Table III. Instruction/Operation Truth Table 1, 2, 3 Instruction Number 0 1 Instruction Byte 0 B23 *********************** B16 C3 C2 C1 C0 A3 A2 A1 A0 0 0 0 0 XXXX 0 0 0 1 0 0 0 A0 Data Byte 1 B15 ***** B8 X *** D9 D8 X *** X X X *** X X Data Byte 0 B7 *** B0 D7 *** D0 X *** X X *** X Operation NOP: Do nothing. See Table XI Write content of EEMEM to RDAC Register. This command leaves device in the Read Program power state. To return part to the idle state, perform NOP instruction #0. See Table XI SAVE WIPER SETTING: Write contents of RDAC to EEMEM. See Table X Write contents of Serial Register Data Bytes 0 and 1 (total 16-bit) to EEMEM(ADDR). See Table XIII Decrement 6 dB: Right Shift contents of RDAC, stops at all "Zeros." Same as instruction 4 Decrement content of RDAC Register by "One," stops at all "Zeros." Same as instruction 6 RESET: Load RDAC with its corresponding EEMEM previously saved value. Write content of EEMEM(ADDR) to Serial Register Data Bytes 0 and 1. SDO activated. See Table XIV Write content of RDAC to Serial Register Data Bytes 0 and 1. SDO activated. See Table XV Write content of Serial Register Data Bytes 0 and 1 (total 10-bit) to RDAC Register. See Table IX Increment 6 dB: Left Shift content of RDAC, stops at all "Ones." See Table XII Same as instruction 12 Increment content of RDAC Register by "One," stops at all "Ones." See Table X. Same as instruction 14 2 34 45 55 65 75 8 9 0 0 1 0 0 0 0 A0 0 0 1 1 A3 A2 A1 A0 X *** X X D15 *** D8 X *** X D7 *** D0 0 1 0 0 0 0 0 A0 0 1 0 1 XXXX 0 1 1 0 0 0 0 A0 0 1 1 1 XXXX 1 0 0 0 XXXX 1 0 0 1 A3 A2 A1 A0 X *** X X X *** X X X *** X X X *** X X X *** X X X *** X X X *** X X *** X X *** X X *** X X *** X X *** X 10 11 125 135 145 155 1 0 1 0 0 0 0 A0 1 0 1 1 0 0 0 A0 X *** X X X *** D9, D8 X *** X D7 *** D0 1 1 0 0 0 0 0 A0 1 1 0 1 XXXX 1 1 1 0 0 0 0 A0 1 1 1 1 XXXX X *** X X X *** X X X *** X X X *** X X X *** X X *** X X *** X X *** X NOTES 1 The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception, any instruction following instruction #9 or #10, the selected internal register data will be present in Data Bytes 0 and 1. The instruction following #9 and #10 must also be a full 24-bit data word to completely clock out the contents of the serial register. 2 The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding nonvolatile EEMEM register. 3 Execution of the above operations takes place when the CS strobe returns to logic high. 4 Instruction #3 write two data bytes (16-Bit data) to EEMEM. In the case of 0 addresses, only the last 10 bits are valid for wiper position setting. 5 The increment, decrement, and shift commands ignore the contents of the shift register Data Bytes 0 and 1. REV. 0 -13- AD5231 ADVANCED CONTROL MODES The AD5231 digital potentiometer contains a set of user programming features to address the wide applications available to these universal adjustment devices. Key programming features include: * Scratch Pad Programming to any desirable values * Nonvolatile memory storage of the present scratch pad RDAC register value into the EEMEM register * Increment and Decrement instructions for RDAC wiper register * Left and right Bit Shift of RDAC wiper register to achieve 6 dB level changes * 28 extra bytes of user-addressable nonvolatile memory Linear Increment and Decrement Commands Table IV. Detail Left and Right Shift Functions for 6 dB Step Increment and Decrement Left Shift 00 0000 0000 00 0000 0001 00 0000 0010 Left Shift (+6 dB/step) 00 0000 0100 00 0000 1000 00 0001 0000 00 0010 0000 00 0100 0000 00 1000 0000 01 0000 0000 10 0000 0000 11 1111 1111 11 1111 1111 Right Shift 11 1111 1111 01 1111 1111 00 1111 1111 00 0111 1111 00 0011 1111 00 0001 1111 00 0000 1111 00 0000 0111 00 0000 0011 00 0000 0001 00 0000 0000 00 0000 0000 00 0000 0000 Right Shift (-6 dB/step) The increment and decrement commands (#14, #15, #6, #7) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the controller to just send an increment or decrement command to the device. For increment command, executing instruction #14 with proper address will automatically move the wiper to the next resistance segment position. Instruction #15 performs the same function except address does not need to be specified. Logarithmic Taper Mode Adjustment ( 6 dB/step) Four programming instructions produce logarithmic taper increment and decrement wiper. These settings are activated by the 6 dB increment and 6 dB decrement instructions #12, #13, #4, and #5, respectively. For example, starting at zero scale, executing 11 times the increment instruction #12 will move the wiper in +6 dB per step from the 0% to full scale RAB. The +6 dB increment instruction doubles the value of the RDAC register content each time the command is executed. When the wiper position is near the maximum setting, the last +6 dB increment instruction will cause the wiper to go to the full-scale 1023 code position. Further +6 dB per increment instruction will no longer change the wiper position beyond its full scale. 6 dB step increment and decrement are achieved by shifting the bit internally to the left and right, respectively. The following information explains the nonideal 6 dB step adjustment at certain conditions. Table IV illustrates the operation of the shifting function on the RDAC register data bits. Each line going down the table represents a successive shift operation. Note that the left shift #12 and #13 commands were modified such that if the data in the RDAC register is equal to zero, and the data is left shifted, the RDAC register is then set to code 1. Similarly, if the data in the RDAC register is greater than or equal to midscale, and the data is left shifted, then the data in the RDAC register is automatically set to full-scale. This makes the left shift function as ideal a logarithmic adjustment as possible. The right shift #4 and #5 commands will be ideal only if the LSB is zero (i.e., ideal logarithmic--no error). If the LSB is a 1, the right shift function generates a linear half LSB error, which translates to a numbers of bits dependent logarithmic error as shown in Figure 8. The plot shows the error of the odd numbers of bits for AD5231. Actual conformance to a logarithmic curve between the data contents in the RDAC register and the wiper position for each Right Shift #4 and #5 command execution contains an error only for odd numbers of bits. Even numbers of bits are ideal. The graph in Figure 8 shows plots of Log_Error [i.e., 20 log10 (error/code)] AD5231. For example, code 3 Log_Error = 20 log10 (0.5/3) = -15.56 dB, which is the worst case. The plot of Log_Error is more significant at the lower codes. 0 -20 dB -40 -60 -80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 103 0.9 1.0 1.1 CODE - From 1 to 1023 by 2.0 Figure 8. Plot of Log_Error Conformance for Odd Numbers of Bits Only (Even Numbers of Bits are Ideal) Using Additional Internal Nonvolatile EEMEM The AD5231 contains additional internal user storage registers (EEMEM) for saving constants and other 16-bit data. Table V provides an address map of the internal storage registers shown in the functional block diagram as EEMEM1, EEMEM2, and 28 bytes (14 addresses 2 bytes each) of User EEMEM. Table V. EEMEM Address Map Address 0000 0001 0010 0011 EEMEM For RDAC1, 2 O1 and O23 USER14 USER2 : 1110 1111 -14- : USER13 USER14 REV. 0 AD5231 NOTES 1 RDAC data stored in EEMEM location is transferred to the RDAC Register at Power ON, or when instructions #1, #8, and PR are executed. 2 Execution of instruction #1 leaves the device in the Read Mode power consumption state. After the last instruction #1 is executed, the user should perform a NOP, instruction #0 to return the device to the low power idling state. 3 O1 and O2 data stored in EEMEM locations are transferred to their corresponding Digital Register at Power ON, or when instructions #1 and #8 are executed. 4 USER are internal nonvolatile EEMEM registers available to store and retrieve constants and other 16-bit information using #3 and #9, respectively. RDAC STRUCTURE The patent pending RDAC contains multiple strings of equal resistor segments, with an array of analog switches, that act as the wiper connection. The number of positions is the resolution of the device. The AD5231 has 1024 connection points allowing it to provide better than 0.1% set-ability resolution. Figure 9 shows an equivalent structure of the connections between the three terminals of the RDAC. The SWA and SWB will always be ON, while one of the switches SW(0) to SW(2N-1) will be ON one at a time depending on the resistance position decoded from the data bits. Since the switch is not ideal, there is a 15 wiper resistance, RW. Wiper resistance is a function of supply voltage and temperature. The lower the supply voltage, or the higher the temperature, the higher the resulting wiper resistance. Users should be aware of the wiper resistance dynamics if accurate prediction of the output resistance is needed. SWA A part. For VDD = 5 V, the wiper first connection starts at the B terminal for data 000H. RWB(0) is 15 because of the wiper resistance and it is independent of the nominal resistance. The second connection is the first tap point where RWB(1) becomes 9.7 + 15 = 27.4 for data 001H. The third connection is the next tap point representing RWB(2) = 19.4 + 15 = 34.4 for data 002H and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at RWB(1023) = 10005 . See Figure 9 for a simplified diagram of the equivalent RDAC circuit. When RWB is used, the A-terminal can be left floating or tied to the wiper. 100 RWA RWA(D), RWB(D) - % of Nominal RAB RWB 75 50 25 0 0 256 512 CODE - Decimal 768 1023 Figure 10. RWA(D) and RWB(D) vs. Decimal Code SW(2N-1) The general equation, which determines the programmed output resistance between W and B, is: W RDAC WIPER REGISTER AND DECODER RS SW(2N- 2) RS SW(1) D (1) x R AB + RW 1024 Where D is the decimal equivalent of the data contained in the RDAC register, RAB is the Nominal Resistance between terminals A-and-B, and RW is the wiper resistance. RWB ( D) = For example, the following output resistance values will be set for the following RDAC latch codes with VDD = 5 V (applies to RAB = 10 k Digital Potentiometers): RS RS = RAB / 2N SW(0) DIGITAL CIRCUITRY OMITTED FOR CLARITY SWB B Table VII. RWB at Selected Codes for RAB = 10 k Figure 9. Equivalent RDAC Structure (Patent Pending) Table VI. Nominal Individual Segment Resistor (R S) D(DEC) RWB(D) () Output State 1023 512 1 0 10,005 50015 24.7 15 Full-Scale MidScale 1 LSB Zero-Scale (Wiper Contact Resistor) Device Resolution 10-Bit 10 k Version 9.8 50 k Version 48.8 100 k Version 97.6 PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation Note that in the zero-scale condition a finite wiper resistance of 15 is present. Care should be taken to limit the current flow between W and B in this state to no more than 20 mA to avoid degradation or possible destruction of the internal switches. Like the mechanical potentiometer the RDAC replaces, the AD5231 parts are totally symmetrical. The resistance between the wiper W and terminal A also produces a digitally controlled complementary resistance RWA. Figure 10 shows the symmetrical programmability of the various terminal connections. When RWA is used, the B-terminal can be let floating or tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general transfer equation for this operation is: -15- The nominal resistance of the RDAC between terminals A-andB, RAB is available with 10 k, 50 k, and 100 k with 1024 positions (10-bit resolution). The final digit(s) of the part number determine the nominal resistance value, e.g., 10 k = 10; 50 k = 50; 100 k = C. The 10-bit data word in the RDAC latch is decoded to select one of the 1024 possible settings. The following discussion describes the calculation of resistance RWB at different codes of a 10 k REV. 0 AD5231 1024 - D (2) x R AB + RW 1024 For example, the following output resistance values will be set for the following RDAC latch codes with VDD = 5 V (applies to RAB = 10 k Digital Potentiometers): RWA ( D) = Table VIII. RWA(D) at Selected Codes for RAB = 10 k Table X. Incrementing RDAC Followed by Storing the Wiper Setting to EEMEM SDI B00100H SDO XXXXXXH Action D(DEC) 1023 512 1 0 RWA(D) () 24.7 5015 10005 10015 Output State Full-Scale MidScale 1 LSB Zero-Scale The typical distribution of RAB from device-to device matches tightly when they are processed at the same batch. When devices are processed at different time, device-to device matching becomes process lot dependent and exhibits a -40% to +20% variation. The change in RAB with temperature has a 600 ppm/C temperature coefficient. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation Loads data 100H into RDAC register, Wiper W moves to 1/4 full-scale position. Increments RDAC register by one E0XXXXH B00100H to 101H. E0XXXXH E0XXXXH Increments RDAC register by one to 102H. Continue until desired wiper position is reached. Saves RDAC register data into 20XXXXH XXXXXXH EEMEM. Optionally tie WP to GND to protect EEMEM values. Table XI. Restoring EEMEM Value to RDAC Register EEMEM value for RDAC can be restored by Power On, or Strobing PR pin, or Programming shown below. SDI SDO Action Restores EEMEM value to RDAC register. NOP. Recommended step to minimize power consumption. Reset EEMEM value to RDAC register. 10XXXXH XXXXXXH 00XXXXH 10XXXXH 8XXXXXH 00XXXXH The digital potentiometer can be configured to generate an output voltage at the wiper terminal which is proportional to the input voltages applied to terminals A and B. For example connecting A-terminal to 5 V and B-terminal to ground produces an output voltage at the wiper which can be any value starting at 0 V up to 5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 2N position resolution of the potentiometer divider. Since AD5231 can also be supplied by dual supplies, the general equation defining the output voltage at VW with respect to ground for any given input voltages applied to terminals A and B is: Table XII. Using Left Shift by One to Increment +6 dB Step SDI SDO Action Moves wiper to double the present data contained in RDAC register. C0XXXXH XXXXXXH D (3) x VAB + VB 1024 Equation 3 assumes VW is buffered so that the effect of wiper resistance is nulled. Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors and not the absolute value, therefore, the drift improves to 15 ppm/C. There is no voltage polarity restriction between terminals A, B, and W as long as the terminal voltage (V TERM) stays within VSS < VTERM < VDD. VW ( D) = PROGRAMMING EXAMPLES Table XIII. Storing Additional User Data in EEMEM SDI 32AAAAH SDO XXXXXXH Action Stores data AAAAH into spare EEMEM location USER1. (Allowable to address in 14 locations with maximum 16 bits of Data.) Stores data 5555H into spare EEMEM location USER2. (Allowable to address in 14 locations with maximum 16 bits of Data.) 335555H 32AAAAH The following programming examples illustrate typical sequence of events for various features of the AD5231. Users should refer to Table III for the instructions and data word format. The Instruction numbers, addresses, and data appearing at SDI and SDO Pins are based in hexadecimal in the following examples. Table IX. Scratch Pad Programming Table XIV. Reading Back Data From Various Memory Locations SDI SDO Action Prepares data read from USER1 location. NOP instruction #0 sends 24-bit word out of SDO where the last 16 bits contain the contents of USER1 location. NOP command ensures device returns to idle power dissipation state. 92XXXXH XXXXXXH 00XXXXH 92AAAAH SDI B00100H SDO XXXXXXH Action Loads data 100H into RDAC register, Wiper W moves to 1/4 full-scale position. -16- REV. 0 AD5231 Table XV. Reading Back Wiper Settings A VIN OFFSET GND DUT B 5V W OP279 VOUT SDI SDO Action Sets RDAC to midscale. Doubles RDAC from midscale to full-scale. (Left shift instructions) Prepares reading wiper setting from RDAC register. Readback full-scale value from RDAC register. B00200H XXXXXXH C0XXXXH B00200H A0XXXXH C0XXXXH XXXXXXH A003FFH OFFSET BIAS Figure 15. Inverting Gain Test Circuit 5V TEST CIRCUITS VIN W OFFSET GND A DUT B OP279 VOUT Figures 11 to 19 define the test conditions used in the product specifications table. NC DUT A W B VMS IW OFFSET BIAS Figure 16. Noninverting Gain Test Circuit +15V W DUT B 2.5V OP42 VOUT A VIN NC = NO CONNECT OFFSET GND Figure 11. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) DUT A V+ B W DUT -15V V+ = V DD 1LSB = V+/2N Figure 17. Gain vs. Frequency Test Circuit RSW = CODE = W B ISW VBIAS 0.1V ISW H VMS + _ 0.1V Figure 12. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL) DUT A VMS2 B VMS1 RW = [V MS1 - V MS2]/ IW W VW IW A = NC Figure 18. Incremental ON Resistance Test Circuit NC VDD DUT VSS GND A W B VCM ICM Figure 13. Wiper Resistance Test Circuit VA V+ = V DD VDD V+ A B 10% PSRR (dB) = 20 LOG PSS (%/%) = VMS% VDD% NC NC = NO CONNECT ~ W VMS ( VMS VDD ) Figure 19. Common-Mode Leakage Current Test Circuit Figure 14. Power Supply Sensitivity Test Circuit (PSS, PSRR) REV. 0 -17- AD5231 FLASH/EEMEM RELIABILITY The Flash/EE Memory array on the AD5231 is fully qualified for two key Flash/EE memory characteristics, namely Flash/EE Memory Cycling Endurance and Flash/EE Memory Data Retention. Endurance quantifies the ability of the Flash/EE memory to be cycled through many Program, Read, and Erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events. These events are defined as: * Initial Page Erase Sequence * Read/Verify Sequence * Byte Program Sequence * Second Read/Verify Sequence During reliability qualification Flash/EE memory is cycled from 000H to 3FFH until a first fail is recorded signifying the endurance limit of the on-chip Flash/EE memory. As indicated in the specification pages of this data sheet, the AD5231 Flash/EE Memory Endurance qualification has been carried out in accordance with JEDEC Specification A117 over the industrial temperature range of -40C to +85C. The results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25C. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the AD5231 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (TJ = 55C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit described above, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its full specified retention lifetime every time the Flash/EE memory is reprogrammed. It should also be noted that retention lifetime, based on an activation energy of 0.6 eV, will derate with TJ as shown in Figure 20. For example, the data is retained for 100 years at 55C operation, but reduces to 15 years at 85C operation. Beyond such limit, the part must be reprogrammed so that the data can be restored. 300 APPLICATIONS Bipolar Operation From Dual Supplies The AD5231 can be operated from dual supplies 2.5 V, which enables control of ground referenced ac signals or bipolar operation. AC signal, as high as VDD/VSS, can be applied directly across terminals A-B with output taking from terminal W. (See Figure 21 for a typical circuit connection.) +2.5V VDD C GND SS SCLK MOSI CS CLK SDI VDD A W GND B VSS 1.25V p-p 2.5V p-p AD5231 D = MIDSCALE -2.5V Figure 21. Bipolar Operation from Dual Supplies High Voltage Operation The Digital Potentiometer can be placed directly in the feedback or input path of an op amp for gain control, provided that the voltage across terminals A-B, W-A, or W-B does not exceed |5 V|. When high voltage gain is needed, users should set a fixed gain in an op amp operated at +15 V, and let the digital potentiometer control the adjustable input. Figure 22 shows a simple implementation. R 2R 15V 5V A - A1 W + V+ V- VO 0 TO 15V AD5231 B Figure 22. 15 V Voltage Span Control Bipolar Programmable Gain Amplifier 250 RETENTION - Years 200 There are several ways to achieve bipolar gain. Figure 23 shows one versatile implementation. Digital potentiometer U1 sets the adjustment range, the wiper voltage V W2 can therefore be programmed between Vi and -KVi at a given U2 setting. For linear adjustment, configure A2 as a noninverting amplifier and the transfer function becomes: ADI TYPICAL PERFORMANCE AT TJ = 55 C 150 100 VO R2 D2 = 1+ x x (1 + K ) - K 1024 Vi R1 where: K is the ratio of RWB/RWA which is set by U1. D = Decimal Equivalent of the Input Code (4) 50 0 40 50 60 70 80 90 TJ JUNCTION TEMPERATURE - C 100 110 Figure 20. Flash/EE Memory Data Retention -18- REV. 0 AD5231 VDD U2 V+ W B Programmable Voltage Reference VO R2 AD5231 A OP2177 V- A2 VSS R1 Vi A B W VDD V+ -kVi U1 AD5231 OP2177 V- A For programmable voltage divider mode operation (Figure 25) it is common to buffer the output of the digital potentiometer unless the load is much larger than the source resistance RWB. In addition, the current handling of the digital potentiometer is limited by its maximum operating voltage, power dissipation, and the maximum current handling of the internal switches at a given resistance (see TPC 20). As a result, the added buffer can be used to deliver the current needed to the load as long as it is within its current handling capability. 5V VSS Figure 23. Bipolar Programmable Gain Amplifier 1 U1 3 AD5231 5V A B W V+ In the simpler (and much more usual) case where K = 1, a pair of matched resistors can replace U1. Equation 4 simplifies to: VIN VOUT VO R2 2 D 2 = 1+ -1 x VI R1 1024 GND AD8601 V- A1 VO (5) 2 AD1582 Table XVI shows the result of adjusting D with A2 configured as a unity gain, a gain of 2, and a gain of 10. The result is a bipolar amplifier with linearly programmable gain and 1024-step resolution. Table XVI. Result of Bipolar Gain Amplifier Figure 25. Programmable Voltage Reference Programmable Voltage Source with Boosted Output D 0 256 512 768 1023 R1 = -1 -0.5 0 0.5 0.992 , R2 = 0 R1 = R2 R2 = 9 R1 -2 -1 0 1 1.984 -10 -5 0 5 9.92 For applications such as laser diode driver or turnable laser, requiring high current adjustment a boosted voltage source can be considered (see Figure 26). VS 5V VBIAS AD5231 A B W A1 R1 10k P1 SIGNAL CC RBIAS IBIAS V+ N1 V- LD 10-Bit Bipolar DAC If the circuit is changed in Figure 23 with the input taking from a voltage reference and configure A2 as a buffer, a 10-bit bipolar DAC can be realized. Compared to the conventional DAC, this circuit offers comparable resolution but not the precision because of the wiper resistance effects. Degradation of the nonlinearity and temperature coefficient are prominent near both ends of the adjustment range. On the other hand, this circuit offers a unique nonvolatile memory feature which in some cases outweigh the shortfall of nonprecision. The output of this circuit is: A1 = AD8601, AD8605, AD8541 P1 = FDP360P, NDS9430 N1 = FDV301N, 2N7002 Figure 26. Boosted Voltage Source 2D2 VO = - 1 x V REF 1024 +5V (6) AD5231 U1 +5V R +2.5VREF W B A R +5V V+ -2.5VREF V+ AD8552 V- A2 -5V VO VIN VOUT TRIM GND In this circuit, the inverting input of the op amp forces the VBIAS to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the P-Ch FET P1. The N-Ch FET N1 simplifies the op amp driving requirement. Resistor R1 is needed to prevent P1 for not turning off once it is on. The choice of R1 is a balance between the power loss of this resistor and the output turn off time. N1 can be any general purpose signal FET; on the other hand, P1 is driven in the saturation state and therefore its power handling must be adequate to dissipate (VS - VBIAS) IBIAS power. This circuit can source maximum of 100 mA at 5 V supply. Higher current can be achieved with P1 in larger package. Note a single N-Ch FET can replace P1, N1, and R1 altogether. However, the output swing will be limited unless separate power supplies are used. For precision application, a voltage reference such as ADR423, ADR292, and AD1584, can be applied at the input of the digital potentiometer. ADR421 AD8552 V- A1 -5V Figure 24. 10-Bit Bipolar DAC REV. 0 -19- AD5231 Programmable 4 mA to 20 mA Current Source A programmable 4 mA to 20 mA current source can be implemented with the circuit shown in Figure 27. +5V 2 VIN 3 SLEEP VOUT 6 U1 0 TO (2.048 + VL) B C1 1F A +5V - W RS 102 R2B in theory can be made as small as needed to achieve the current needed within A2 output current driving capability. In this circuit OP2177 delivers 5 mA in both directions and the voltage compliance approaches 15 V. It can be shown that the output impedance is: ZO = REF191 GND 4 R1 R1 x R2' - 1 R1' x R2 (9) AD5231 -2.048V TO VL V+ U2 ZO can be infinite if resistors R1 and R2 match precisely with R1 and R2A + R2B respectively. On the other hand, ZO can be negative if the resistors are not matched. As a result, C1 and C2, in the range of 1 pF to 10 pF, are needed to prevent the oscillation. Resistance Scaling VL OP1177 + RL 100 R2 15k +15V - +2.5V A AD5231 BW -2.5V V+ R2B 50 C1 10pF OP2177 + V- A2 C2 10pF -15V R1 150k R2A 14.95k VL RL 500 IL V- -5V IL Figure 27. Programmable 4 mA to 20 mA Current Source REF191 is a unique low supply headroom precision reference that can deliver the 20 mA needed at 2.048 V. The load current is simply the voltage across terminals B-to-W of the digital potentiometer divided by RS: AD5231 offers 10 k, 50 k, and 100 k nominal resistance. For users who need lower resistance but want to maintain the numbers of step adjustment, they can parallel multiple devices. For example, Figure 29 shows a simple scheme of paralleling two AD5231. In order to adjust half of the resistance linearly per step, users need to program both devices coherently with the same settings and tie the terminals as shown. A1 A2 W1 B2 W2 V x D I L = REF RS (7) B1 LD The circuit is simple, but be aware that there are two issues. First, dual supply op amps are ideal because the ground potential of REF191 can swing from -2.048 V at zero scale to VL at full scale of the potentiometer setting. Although the circuit works under single supply, the programmable resolution of the system will be reduced. Second, the voltage compliance at VL is limited to 2.5 V or equivalently a 125 load. Should higher voltage compliance be needed, users may consider digital potentiometers AD5260, AD5280, and AD7376. Figure 28 below shows an alternate circuit for high voltage compliance. Programmable Bidirectional Current Source Figure 29. Reduce Resistance by Half with Linear Adjustment Characteristics In voltage divider mode, a much lower resistance can be achieved by paralleling a discrete resistor as shown in Figure 30. The equivalent resistance become: RWBeq = D ( R1 / / R2) + RW 1024 (10) (11) D RWA = 1 - ( R1 / / R2) + RW eq 1024 A For applications that require bidirectional current control or higher voltage compliance, a Howland current pump can be a solution. If the resistors are matched, the load current is: ( R2 A + R2 B) IL = R1 R2 B x VW R1 150k R2 R1 W (8) B R2 << R1 Figure 30. Lowering the Nominal Resistance Figures 29 and 30 show that the digital potentiometers change steps linearly. On the other hand, log taper adjustment is usually preferred in applications like audio control. Figure 31 shows another way of resistance scaling. In this configuration, the smaller the R2 with respect to R1, the more the pseudo log taper characteristic behaves. +15V + V+ OP2177 - V- A1 -15V Figure 28. Programmable Bidirectional Current Source -20- REV. 0 AD5231 A R1 B W R2 VO Listing I. Macro Model Net List for RDAC .PARAM D = 1024, RDAC = 10E3 * .SUBCKT DPOT (A, W, B) Figure 31. Resistor Scaling with Pseudo Log Adjustment Characteristics RDAC CIRCUIT SIMULATION MODEL * CA RAW CW RBW CB A A W W B 0 W 0 B 0 50E-12 {(1-D/1024)*RDAC+15} 50E-12 {D/1024*RDAC+15} 50E-12 The internal parasitic capacitances and the external load dominates the ac characteristics of the RDACs. Configured as a potentiometer divider the -3 dB bandwidth of the AD5231BRU10 (10 k resistor) measures 370 kHz at half scale. TPC 10 provides the large signal BODE plot characteristics. A parasitic simulation mode is shown in Figure 32. Listing I provides a macro model net list for the 10 k RDAC: RDAC 10k A CA 50pF B CB 50pF * .ENDS DPOT CW 50pF W Figure 32. RDAC Circuit Simulation Model for RDAC = 10 k REV. 0 -21- AD5231 DIGITAL POTENTIOMETER FAMILY SELECTION GUIDE Number Part of VRs per Number Package AD5201 1 Terminal Voltage Range (V) 3, +5.5 Interface Data Control 3-Wire Nominal Resistance (k ) 10, 50 Resolution (Number of Wiper Positions) 33 Power Supply Current (IDD) ( A) Packages 40 SOIC-10 Comments Full ac Specs, Dual Supply, Power-On Reset, Low Cost No Rollover, Power-On Reset Single 28 V or Dual 15 V Supply Operation Full ac Specs, Dual Supply, Power-On Reset Full ac Specs 5 V to 15 V or 5 V Operation, TC < 50 ppm/C I2C Compatible, TC < 50 ppm/C Nonvolatile Memory, Direct Program, I/D, 6 dB Settability No Rollover, Stereo Power-On Reset, TC < 50 ppm/C Full ac Specs, nA Shutdown Current Full ac Specs, Dual Supply, Power-On Reset, SDO Nonvolatile Memory, Direct Program, I/D, 6 dB Settability Nonvolatile Memory, Direct Program, TC < 50 ppm/C I2C Compatible, TC < 50 ppm/C 5 V to 15 V or 5 V Operation, TC < 50 ppm/C Full ac Specs, nA Shutdown Current Nonvolatile Memory, Direct Program, I/D, 6 dB settability Full ac Specs, Dual Supply, Power-On Reset Full ac Specs, nA Shutdown Current Full AC specs, Dual Supply, Power-On Reset AD5220 AD7376 1 1 5.5 15, +28 3, +5.5 UP/ DOWN 3-Wire 10, 50, 100 10, 50, 100, 1000 10, 50 128 128 40 100 PDIP, SO-8, SOIC-8 PDIP-14, SOL-16, TSSOP-14 SOIC-10 AD5200 1 3-Wire 256 40 AD8400 AD5260 1 1 5.5 5, +15 3, +5.5 2.75, +5.5 3-Wire 3-Wire 1, 10, 50, 100 20, 50, 200 256 256 5 60 SO-8 TSSOP-14 AD5241 AD5231 1 1 2-Wire 3-Wire 10, 100, 1000 10, 50, 100 256 1024 50 20 SO-14, TSSOP-14 TSSOP-16 AD5222 2 3, +5.5 UP/ DOWN 3-Wire 3-Wire 10, 50, 100, 1000 1, 10, 50, 100 10, 50, 100 128 80 SO-14, TSSOP-14 PDIP, SO-14, TSSOP-14 TSSOP-14 AD8402 AD5207 2 2 5.5 3, +5.5 2.75, +5.5 2.75, +5.5 3, +5.5 5, +15 256 256 5 40 AD5232 2 3-Wire 10, 50, 100 256 20 TSSOP-16 AD5235 2 3-Wire 25, 250 1024 20 TSSOP-16 AD5242 AD5262 2 2 2-Wire 3-Wire 10, 100, 1000 20, 50, 200 256 256 50 60 SO-16, TSSOP-16 TSSOP-16 AD5203 4 5.5 3-Wire 10, 100 64 5 PDIP, SOL-24, TSSOP-24 TSSOP-24 AD5233 4 2.75, +5.5 3, +5.5 3-Wire 10, 50, 100 64 20 AD5204 4 3-Wire 10, 50, 100 256 60 PDIP, SOL-24, TSSOP-24 PDIP, SOL-24, TSSOP-24 PDIP, SOL-24, TSSOP-24 AD8403 4 5.5 3-Wire 1, 10, 50, 100 256 5 AD5206 6 3, +5.5 3-Wire 10, 50, 100 256 60 -22- REV. 0 AD5231 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead TSSOP (RU-16) 0.201 (5.10) 0.193 (4.90) 16 9 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 8 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX SEATING PLANE 8 0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) 0 BSC 0.0075 (0.19) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) REV. 0 -23- -24- C02739-.8-10/01(0) PRINTED IN U.S.A. |
Price & Availability of AD5231BRU100-REEL7
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